./../../example_design/bench/ddr3_tb/ddr_test_top_tb.v
./../../example_design/bench/mem/ddr3.v
./../../example_design/bench/mem/ddr3_parameters.vh
./../../example_design/rtl/axi_bist_top_v1_0.v
./../../example_design/rtl/prbs15_64bit_v1_0.v
./../../example_design/rtl/prbs31_128bit_v1_0.v
./../../example_design/rtl/test_ddr.v
./../../example_design/rtl/test_main_ctrl_v1_0.v
./../../example_design/rtl/test_rd_ctrl_v1_0.v
./../../example_design/rtl/test_wr_ctrl_v1_0.v
./../../example_design/rtl/uart_rd_lock.v
./../../example_design/rtl/uart_ctrl_32bit/ipsxb_clk_gen_32bit.v
./../../example_design/rtl/uart_ctrl_32bit/ipsxb_cmd_parser_32bit.v
./../../example_design/rtl/uart_ctrl_32bit/ipsxb_seu_rs232_intf.v
./../../example_design/rtl/uart_ctrl_32bit/ipsxb_seu_uart_rx.v
./../../example_design/rtl/uart_ctrl_32bit/ipsxb_seu_uart_tx.v
./../../example_design/rtl/uart_ctrl_32bit/ipsxb_uart_ctrl_32bit.v
./../../example_design/rtl/uart_ctrl_32bit/ipsxb_uart_ctrl_top_32bit.v
./../../example_design/rtl/uart_ctrl_32bit/ipsxb_ver_ctrl_32bit.v
./../../rtl/ipsxb_rst_sync_v1_1.v
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_calib_mux_v1_3.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_calib_top_v1_3.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_control_path_adj_v1_0.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_data_slice_v1_4.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_dfi_v1_4.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_dll_update_ctrl_v1_0.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_drift_ctrl_v1_3.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_gate_update_ctrl_v1_3.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_init_v1_0.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_main_ctrl_v1_3.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_rdcal_v1_2.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_rst_debounce_v1_0.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_slice_rddata_align_v1_0.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_training_ctrl_v1_0.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_upcal_v1_4.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_wdata_path_adj_v1_0.vp
./../../sim_lib/rtl/ddrphy/ipsxb_ddrphy_wrlvl_v1_0.vp
./../../rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v
./../../rtl/pll/ipsxb_ddrphy_pll_v1_0.v
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_apb_cross_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_calib_delay_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_cfg_apb_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_bm_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_rowaddr_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_top_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_buf_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_out_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_top_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_lp_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_mrs_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_prefetch_fifo_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_rdatapath_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_wdatapath_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_wdp_align_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_wdp_dcp_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/ipsxb_mcdq_wrapper_v1_2a.vp
./../../sim_lib/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_tfaw_timing_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_tfaw_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_act2wr_pass_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_act_pass_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_pre_pass_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_rd_pass_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_ref_pass_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_wr_pass_v1_2.vp
./../../sim_lib/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_trc_timing_v1_2.vp
./../../rtl/mcdq_ctrl/distributed_fifo/ipsxb_distributed_fifo_v1_0.v
./../../rtl/mcdq_ctrl/distributed_fifo/rtl/ipsxb_distributed_fifo_ctr_v1_0.v
./../../rtl/mcdq_ctrl/distributed_fifo/rtl/ipsxb_distributed_fifo_v1_0_distributed_fifo_v1_0.v
./../../rtl/mcdq_ctrl/distributed_fifo/rtl/ipsxb_distributed_sdpram_v1_0_distributed_fifo_v1_0.v
C:/pango/PDS_2022.1/ip/system_ip/ipsxb_hmic_s/ipsxb_hmic_eval/ipsxb_hmic_s/../../../../../arch/vendor/pango/verilog/simulation/GTP_DLL.v
C:/pango/PDS_2022.1/ip/system_ip/ipsxb_hmic_s/ipsxb_hmic_eval/ipsxb_hmic_s/../../../../../arch/vendor/pango/verilog/simulation/GTP_DDC_E1.v
C:/pango/PDS_2022.1/ip/system_ip/ipsxb_hmic_s/ipsxb_hmic_eval/ipsxb_hmic_s/../../../../../arch/vendor/pango/verilog/simulation/GTP_OSERDES.v
C:/pango/PDS_2022.1/ip/system_ip/ipsxb_hmic_s/ipsxb_hmic_eval/ipsxb_hmic_s/../../../../../arch/vendor/pango/verilog/simulation/GTP_OUTBUFT.v
C:/pango/PDS_2022.1/ip/system_ip/ipsxb_hmic_s/ipsxb_hmic_eval/ipsxb_hmic_s/../../../../../arch/vendor/pango/verilog/simulation/GTP_OUTBUFTCO.v
C:/pango/PDS_2022.1/ip/system_ip/ipsxb_hmic_s/ipsxb_hmic_eval/ipsxb_hmic_s/../../../../../arch/vendor/pango/verilog/simulation/GTP_GRS.v
C:/pango/PDS_2022.1/ip/system_ip/ipsxb_hmic_s/ipsxb_hmic_eval/ipsxb_hmic_s/../../../../../arch/vendor/pango/verilog/simulation/GTP_CLKBUFG.v
C:/pango/PDS_2022.1/ip/system_ip/ipsxb_hmic_s/ipsxb_hmic_eval/ipsxb_hmic_s/../../../../../arch/vendor/pango/verilog/simulation/GTP_PLL_E3.v
C:/pango/PDS_2022.1/ip/system_ip/ipsxb_hmic_s/ipsxb_hmic_eval/ipsxb_hmic_s/../../../../../arch/vendor/pango/verilog/simulation/GTP_IOCLKBUF.v
C:/pango/PDS_2022.1/ip/system_ip/ipsxb_hmic_s/ipsxb_hmic_eval/ipsxb_hmic_s/../../../../../arch/vendor/pango/verilog/simulation/GTP_IOCLKDIV.v
C:/pango/PDS_2022.1/ip/system_ip/ipsxb_hmic_s/ipsxb_hmic_eval/ipsxb_hmic_s/../../../../../arch/vendor/pango/verilog/simulation/GTP_IOBUFCO.v
C:/pango/PDS_2022.1/ip/system_ip/ipsxb_hmic_s/ipsxb_hmic_eval/ipsxb_hmic_s/../../../../../arch/vendor/pango/verilog/simulation/GTP_IOBUF.v
C:/pango/PDS_2022.1/ip/system_ip/ipsxb_hmic_s/ipsxb_hmic_eval/ipsxb_hmic_s/../../../../../arch/vendor/pango/verilog/simulation/GTP_IODELAY.v
C:/pango/PDS_2022.1/ip/system_ip/ipsxb_hmic_s/ipsxb_hmic_eval/ipsxb_hmic_s/../../../../../arch/vendor/pango/verilog/simulation/GTP_ISERDES.v
./../../DDR3_50H.v
./../../DDR3_50H_ddrphy_top.v
 
+define+SIMULATION  
+define+den4096Mb   
+define+sg25E       
+define+x16         
